1. Field of the Invention
The present invention relates to multi-plane video displays. More particularly, the present invention relates to a page mode memory controller for providing a plurality of display planes during each image memory access cycle.
2. Description of the Prior Art
The desire to convert data into graphic forms that can be readily manipulated is making graphics capabilities a requirement of many computer customers. Providing color in a product is even more desirable because color adds clarity throughout a presentation and emphasizes key points.
An inexpensive and easy way to add graphics-like functions to an existing design is to enhance the character set by adding one or more ROMs or PROMs. Line drawing sets are created this way, as are some of the "graphics" on personal computers. For simple forms generation or very simple bar charts this approach may be adequate. Adding character set memory requires little or no redesign of the alphanumeric display structure and is therefore quick to implement. But it is also inflexible since only predesignated graphic symbols are available--no combining or overlaying of the symbols is possible.
To increase flexibility, a RAM-based character set with an option to reload the character set or add more RAM for "user-defined" characters is often used. This allows a user the flexibility necessary to design charater cells that fit specific applications. For simple bar charts and pictures, where the necessary character cells are repetitive, this is usually sufficient. For more complex pictures, where the frequency of repetition of character cells is lower, the user may not have enough unique characters to complete the picture or graph. If there are not enough unique characters, the user must simplify the chart, leaving out potentially valuable detail. To guarantee a sufficiently large number of unique characters requires a large RAM array with a short access time, thus eliminating the cost advantage of this structure.
Because of the problems associated with making enhanced character mode displays work for even moderately complex pictures and graphs, most raster-scan graphic implementations are bit-mapped. In a bit-mapped graphics system, displaying complex pictures and graphs containing a lot of information is no more difficult than displaying simple pictures and graphs containing little information.
In a bit-mapped graphics system, a RAM array having a one-to-one correspondence with the visible image on the display is used to store the graphic image. The array must be controllable in two ways. First, the data in the array must be read and sent to the CRT or other raster display. Second, the array must be modifiable so that storing a picture or graph is not difficult. Some bit-mapped graphics systems are organized as dual-port memories having one address port for the display addressing and another port for image generation. Most systems share a single address port with one function having priority.
The design of a controller for a graphics bit map system requires an understanding of the overall system function. Graphics systems must to be able to take objects and modify them and their characteristics on a display. Objects may be structured, that is, contain other objects, or they may be simple collections of vectors, arcs, and other primitive elements. These primitives must be manipulated to translate (move horizontally and vertically), rotate, scale (change the relative size on the screen), and clip (delete invisible portions) the objects as the image is moved about on the screen. Once the vectors or arcs that are to be displayed are determined, such information is converted into locations and data to be written. The process of converting vector information to raster RAM addresses is known as "vector-to-raster" conversion.
There are numerous ways to partition the sequence of tasks associated with conversion of data to pictures or charts. The most common way accomplishes all computations with one processor. For large mainframe systems the host computer does all the computations and a "dumb terminal" holds the display. Personal computers take a similar approach on the opposite end of the scale. All system functions, including all levels of graphic functions, are done with a MOS microprocessor.
Other partitioning include using a general purpose MOS microprocessor to handle system functions while a specialized finite state machine controls a set of registers, counters, and adders that handle vector-to-raster conversion. This approach adds a first level of pipelining that increases throughput, but it also increases the amount of hardware needed. Substituting a MOS microprocessor to handle low level graphics manipulation--in addition to vector-to-raster conversion--increases system flexibility and potential capability with little sacrifice in system speed. Substituting a bipolar bit-slice processor for either microprocessor increases throughput proportional to the increased processing speed. A problem with this approach is that bit-slice processor systems typically require excessive space and power.
Providing three levels of pipelining by separating vector-to-raster conversion/vector transformation from other system functions, has a similar effect--an increase in speed, but an additional space and power penalty. In general, all previously known approaches are less than satisfactory because they use general purpose ICs and processors, which are optimized for functions other than graphics.